Dr. Peter Baumgartner (Intel), Dr.-Ing. Kateryna Smirnova 

Arbeitsort: Intel, München 

With increasing operating frequencies and continuous miniaturization of electronics, transistors are packed densely into increasingly compact areas, significantly raising power densities. This leads to transient self-heating effects in transistors, altering device characteristics and impacting circuit operation. Accurate modeling of self-heating in circuit simulations requires precise characterization data. However, obtaining such data is increasingly challenging due to the extremely short time scales in advanced transistor devices such as 3D FinFets and Gate All Around Fets.

This effect is investigated using both modeling approaches and experimental methods. Some of the existing characterization techniques involve the extraction of thermal parameters using the AC-DC mixed method or pulsed measurements [1,2].

The goal of this master thesis is to compare different characterization methods for analyzing the self-heating effect in advanced FinFet technologies and prepare the methods for Gate All Around technologies.

Requirements: ES, RFE

[1] I. Hasnaoui, A. Pottrain, D. Gloria, P. Chevalier, V. Avramovic and C. Gaquiere, "Self-Heating Characterization of SiGe:C HBTs by Extracting Thermal Impedances," in IEEE Electron Device Letters, vol. 33, no. 12, pp. 1762-1764, Dec. 2012, doi: 10.1109/LED.2012.2220752.

[2] U. Monga, J. Aghassi, D. Siprak, J. Sedlmeir, C. Hanke, V. Kubrak, R. Heinrich, and T. A. Fjeldly, "Impact of Self-Heating in SOI FinFETs on Analog Circuits and Interdie Variability," IEEE Electron Device Letters, vol. 32, no. 3, pp. 249-251, Mar. 2011, doi: 10.1109/LED.2010.2097235.