M.Eng. Elizabeth Bekker

Dr.-Ing. Akanksha Bhutani

Abstract:

Advances in MMIC technology have made it possible to integrate entire radar systems on a single chip. The use of millimetre wave frequencies has reduced the size of the antenna, allowing it to be either on-chip or integrated into a package. Flip-chip interconnects ensure compact package size while maintaining low loss over a wide bandwidth. As flip-chip interconnects are the key to compact millimetre-wave radar packages, this work focuses on their electrical and mechanical aspects for D-band applications. A lumped element model was derived and a parameter study linked the physical dimensions of the transition to the components of the model. The results were used to optimise the electrical performance of the transition. Fabrication cost of the flip-chip packages was kept low by only using a laser for structuring, a wirebonder for flip-chip bumping and a flip-chip aligner bonder. The flip-chip interconnects were made by placing gold bumps on the gold pads of the package and attaching the chip using thermosonic flip-chip bonding. Thermosonic bonding requires less temperature than termocompression bonding and is more robust against surface contaminations. Several experiments with RO4003C as a substrate have shown that its relatively thick metal stack caused problems with laser structuring and bond quality. Alumina with 4 μm gold cladding was then used as an alternative. Bond failures were minimized with a better cleaning process that involves polishing the metallisation and ultrasonic cleaning before bonding. To investigate inductive compensation of the capacitance introduced by flip-chip interconnects by increased ground bump spacing, three different back-to-back flip-chip packages were manufactured with different spacings. Each series consists of three samples, which gives 9 samples in total. The S-parameters of all packages were measured from DC to 170 GHz. Every test structure worked and samples within a series showed very similar S-parameters, which indicates that the process control is sufficient to get reproducible results. Maximum S11 over the entire frequency span of all packages is −6 dB and maximum S21 is −3.2 dB. The measurement includes the CPWs before/after and between the flip-chip interconnects (total CPW length = 4mm). The characteristic impedance of the manufactured CPWs was found to be 65Ω, which caused increased reflection at the transitions. The effect of increased bump spacing was smaller than expected. S21 improved on average by 0.12 dB for a wide bump spacing compared to a narrow spacing.